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5.16. JTAG Operations
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The ? i.MX53 ? Applications ? Processor ? accepts ? five ? JATG ? signals ? from ? an ? attached ? debugging ? device ? on ?
dedicated ? pins. ? A ? sixth ? pin ? on ? the ? processor ? accepts ? a ? board ? HW ? configured ? input ? specific ? to ? the ? Quick ?
Start ? board ? only. ? The ? five ? JTAG ? signal ? used ? by ? the ? Processor ? are: ?
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JTAG_TCK ?
JTAG_TMS ?
JTAG_TDI ?
JTAG_TDO ?
JTAG_nTRST ?
TAP ? Clock ?
TAP ? Machine ? State ?
TAP ? Data ? In ?
TAP ? Data ? Out ?
TAP ? Reset ? Request ? (Active ? Low) ?
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The ? TAP ? Clock ? signal ? is ? provided ? by ? the ? attached ? debugging ? device ? and ? serves ? as ? a ? reference ? for ? data ?
exchange ? between ? the ? debugging ? device ? and ? the ? Processor. ? The ? TAP ? Machine ? State ? is ? a ? logical ? signal ?
provided ? by ? the ? debugging ? device ? to ? let ? the ? Processor ? (or ? Target) ? know ? what ? state ? to ? enter ? next. ? Per ?
JATG ? specifications, ? all ? questions ? of ? state ? have ? two ? options ? that ? can ? be ? selected ? with ? either ? a ? ‘high’ ? or ??
‘low’ ? signal. ? The ? TAP ? Data ? In ? and ? TAP ? Data ? Out ? signal ? are ? used ? only ? for ? data ? transfer. ?
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The ? Active ? Low ? TAP ? Reset ? Request ? is ? initiated ? by ? the ? debugging ? device ? and ? resets ? the ? TAP ? (JTAG) ?
module ? within ? the ? Processor. ? This ? gives ? the ? debugging ? device ? the ? ability ? to ? reset ? the ? internal ? Processor ?
JTAG ? module ? if ? required ? without ? affecting ? the ? remainder ? of ? the ? Processor. ?? The ? system ? JTAG ? reset ? signal ?
provided ? by ? the ? attached ? debugging ? device ? does ? not ? go ? to ? the ? JTAG ? module ? of ? the ? processor, ? but ? goes ?
to ? the ? external ? processor ? reset ? circuitry ? which ? will ? fully ? reset ? the ? i.MX53 ? processor, ? but ? not ? the ? power ?
rails. ?
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The ? JTAG_MOD ? pin ? used ? by ? the ? JTAG ? module ? of ? the ? i.MX53 ? Processor ? determines ? how ? much ? of ? the ?
i.MX53 ? processor ? is ? connected ? to ? the ? JTAG ? Debugging ? device. ? In ? the ? pull ‐ down ? mode ? (default ? on ? the ?
Quick ? Start ? board) ? allows ? all ? of ? the ? i.MX53 ? TAPs ? (SJC, ? SDMA, ? ARM) ? to ? be ? connected ? to ? the ? debugging ?
device ? in ? a ? daisy ? chain ? connection. ? If ? the ? JTAG_MOD ? pin ? is ? pulled ? high, ? then ? the ? attached ? debugging ?
device ? can ? only ? access ? the ? SJC ? TAP. ?
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Three ? other ? common ? JTAG ? signals ? used ? by ? debugging ? devices ? (Return ? Clock, ? Data ? Enable, ? and ? Data ?
Acknowledge) ? are ? not ? used ? by ? the ? i.MX53 ? Applications ? Processor ? and ? are ? either ? pulled ‐ up ? or ? pulled ‐
down ? by ? the ? Quick ? Start ? board. ?
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On ? the ? Quick ? Start ? board, ? the ? logic ? signals ? for ? JTAG ? are ? designed ? to ? be ? 1.8V. ? A ? 1.8V ? reference ? signal ? from ?
VLDO8_1V8 ? is ? connected ? to ? pin ? 1 ? of ? the ? 20 ‐ pin ? JTAG ? connector ? to ? provide ? this ? logic ? level ? signal ? to ? the ?
attached ? debugging ? device. ? In ? addition, ? for ? debugging ? devices ? that ? required ? power, ? a ? limited ? amount ?
(~0.5 ? A) ? of ? 3.2V ? power ? can ? be ? supplied ? to ? the ? debugging ? device. ? If ? the ? device ? requires ? 1.8V ? power ?
(instead ? of ? 3.2V ? power), ? the ? Quick ? Start ? board ? can ? be ? configured ? to ? supply ? this ? as ? well, ? but ? in ? a ? very ?
limited ? amount ? (100 ? mA). ?
Freescale Semiconductor
Hardware User Guide for i.MX53 Quick Start Board,
Preliminary Rev 0.91
62
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